# pcie7 **Repository Path**: dnknow/pcie7 ## Basic Information - **Project Name**: pcie7 - **Description**: PCIe Module LOGs [2023] speedz@tutanota.com - **Primary Language**: Unknown - **License**: Not specified - **Default Branch**: master - **Homepage**: None - **GVP Project**: No ## Statistics - **Stars**: 0 - **Forks**: 1 - **Created**: 2023-05-10 - **Last Updated**: 2023-09-21 ## Categories & Tags **Categories**: Uncategorized **Tags**: None ## README # PCIe Module Work Summary in 2023 ## 🦀 2023.02 + 2023.03 - Get familiar with function requirements of the PCIe block. - Read Controller IP PDFs and C10 PHY IP PDFs. - Setup dev. environment (CTL 6.00a/VIP/C10 PHY 1.09b) - Release 202 PCIe CoreCfg_v1_0 with new settings from scratch based on CTL IP 6.00a. CoreCfg_v1_0 makes the following enhancements/debugs: [**EnhID1**] AER [**EnhID4**] RAS [**EnhID6**] Native HDMA [**BugID2**] Optimize Receive Completion Queue Mode (VC0) [**BugID4**] Full NCBE support [**EnhID7**] Proven Bandwidth match between PCIe and AXI based on simulation. File: **[bandwidth test](https://gitee.com/speedz/pcie7/tree/master/CoreCfg/cfg_v1_0/bandwidth)** File: **[cfg_v1_0 tcl script](https://gitee.com/speedz/pcie7/tree/master/CoreCfg/cfg_v1_0)** (zip with password) ## 🦑 2023.04 - [**BugID2**] Write testbench to simulate PCIe core behavior: inbound P + outbound NP bandwidth test. It's proven that CPLs of OB NP-requests will NOT be blocked by IB P-requests within the PCIe core. File: **[html version](https://gitee.com/speedz/pcie7/blob/master/DebugList/BugID2/readme.md)** or **[pdf version](https://gitee.com/speedz/pcie7/blob/master/DebugList/BugID2/CPL_TLPs_delivery_readme.pdf)** - [**BugID4**] Collect trace information about 3D/2D GPU's AXI NCBE write transactions. - [**BugID4**] Write testbench to verify PCIe core behavior: PCIe request conversion rule of outbound AXI NCBE writes and analysis of the performance impact. File: **[NCBE html version](https://gitee.com/speedz/pcie7/blob/master/DebugList/BugID4/readme.md)** or **[NCBE pdf version](https://gitee.com/speedz/pcie7/blob/master/DebugList/BugID4/NCBE_readme.pdf)** - [**EnhID4**] Simulate RAS D.E.S. File: **[RAS readme](https://gitee.com/speedz/pcie7/blob/master/EnhancementList/EnhID4/readme.md)** - [**EnhID1**] Simulate AER, and write AER driver support guide. File: **[AER driver support guide](https://gitee.com/speedz/pcie7/blob/master/EnhancementList/EnhID1/readme.md)** - [**EnhID2**] Simulate Multiple MSI. File: **[Multiple MSI Considerations](https://gitee.com/speedz/pcie7/blob/master/EnhancementList/EnhID2/Multiple_MSI_Considerations.md)** - Release 202 PCIe CoreCfg_v1_1 with minor changes. File: **[cfg_v1_1 tcl script](https://gitee.com/speedz/pcie7/tree/master/CoreCfg/cfg_v1_1)** (zip with password) ## 🛳 2023.05 - Release 202 PCIe CoreCfg_v1_2 with minor changes. File: **[cfg_v1_2 tcl script](https://gitee.com/speedz/pcie7/tree/master/CoreCfg/cfg_v1_2)** (zip with password) - [**HowID1**] How to set the number of lanes in the PCIe link (requested by Hu-YM). File: **[how to set lane number](https://gitee.com/speedz/pcie7/tree/master/HowtoList/HowID1/readme.md)** - [**EnhID10**] Function Level Reset (FLR). File: **[FLR considerations](https://gitee.com/speedz/pcie7/blob/master/EnhancementList/EnhID10/readme.md)** - [**201CodeExplore**] 201 interrupt known issues and fixes. File: **[201_interrupt_known_issues_fixes](https://gitee.com/speedz/pcie7/blob/master/201Explore/201_interrupt_known_issues.md)** ## 🏄 2023.06 - [**201CodeExplore**] 201 on-chip-bus latency. File: **[201_high_latency_on-chip-bus_data-path_for_register_access](https://gitee.com/speedz/pcie7/blob/master/201Explore/201_high_latency_on-chip-bus_data-path_for_register_access.md)** - [**201CodeExplore**] 201 device initialization time limit. File: **[201_initialization_time_limit](https://gitee.com/speedz/pcie7/blob/master/201Explore/201_initialization_time_limit.md)** - [**EnhID2**] 202 New Feature: Add Multiple MSI Support. File: **[202_Multiple_MSI_Support_Guide](https://gitee.com/speedz/pcie7/blob/master/EnhancementList/EnhID2/202_Multiple_MSI_Support.md)** ## 🦑 2023.07 - [**201CodeExplore**] 201 PCIe PHY Reference Clock. A x16 PCIe PHY consists of 4 sub-phy blocks, that each has a pair of differential reference clock input. The 201 chip design uses 4 pairs of PCIe reference clock input (Need 8 PADs). Why not to use a single pair of clock input, then feed it to the on-chip 4 sub-phy blocks (Only need 2 PADs)? - [**201CodeExplore**] 201 PCIe PHY Reference Resistor. An external reference resistor is used for calibration of PHY RX and TX termination. A x16 PCIe PHY consists of 4 sub-phy blocks, that each sub-phy block has a reference resistor input. The default synopsys x16 PHY RTL design uses a single reference resistor, sharing is supported by daisy-chaining the res_req_in/out and res_ack_in/out signals (Need 1 PAD). But 201 chip design disables reference resistor sharing intentionally, and uses 4 reference resistors (Need 4 PADs). why ? In upcs synth script, set DWC_PHY_SEP_RESREF=0 to enable shared resref. In the original script, DWC_PHY_SEP_RESREF=1 by default. - [**201CodeExplore**] 201 PCIe PHY Firmware Updating. The 201 PCIe PHY supports PMA firmware updating after silicon tapout. The firmware content must be written into 4 PHY SRAMs before PCIe training start. To load the firmware as quickly as possible: -- Use a faster phy_cr_clock. -- Use broadcast write to load firmware into 4 SRAMs simultaneously. - [**201CodeExplore**] 201 PCIe PHY software Configuration. 201 chip design exposes some phy configuration signals (e.g MPLL) to software controllable registers (e.g. protocl0_ext_* signals). I don't think it may have any benifit from doing that, because: -- The PCS drives the configuration inputs to the PHY using predefined and prevalidated settings. You don't need to set them manually. -- The configuration setting signals can be overriden by users, and after programming, a phy_reset must be performed to let the new configuration take effect. But the phy_reset in 201 chip is NOT controllable by software. ## 🛳 2023.08 - [**202Code**] Lint 202 PCIe block RTL using VC SpyGlass - [**202Code**] 202 PCIe PHY Function Mode SDC ``` Function mode SDC reference: dwc_c10pcie3phy_tsmc16ffc_x4ns/1.09b/macro/spyglass/manual.sgdc # Global set_case_analysis section # Disable all test modes if { $SG_DESIGN_MODE != "ANA_TYPEC" } { set_case_analysis -name "phy0_scan_pma_occ_en" -value 0 } set_case_analysis -name "pcs_scan_mode" -value 0 set_case_analysis -name "pcs_scan_rst" -value 0 set_case_analysis -name "pcs_scan_shift" -value 0 set_case_analysis -name "pcs_scan_shift_cg" -value 0 set_case_analysis -name "phy_test_burnin" -value 0 set_case_analysis -name "phy_test_powerdown" -value 0 set_case_analysis -name "phy*_scan_mode" -value 0 set_case_analysis -name "phy*_scan_shift" -value 0 set_case_analysis -name "phy*_scan_shift_cg" -value 0 set_case_analysis -name "phy*_scan_set_rst" -value 0 set_case_analysis -name "phy*_bs_ce" -value 0 set_case_analysis -name "phy*_test_tx_ref_clk_en" -value 0 set_case_analysis -name "phy*_test_flyover_en" -value 0 set_case_analysis -name "phy*_test_stop_clk_en" -value 0 ``` - [**202Code**] 202 PCIe PHY scan clock groups ``` scan clock group reference: dwc_c10pcie3phy_tsmc16ffc_x4ns/1.09b/pma/atpg/11M_2Xa1Xd_h_3Xe_vhv_2Y2R/tetramax/clock_group.tcl ```