# Pipeline CPU based on FPGA and Verilog.（基于FPGA的流水线CPU）

**Repository Path**: quanquaqu/pipelinecpu-fpga-verilog

## Basic Information

- **Project Name**: Pipeline CPU based on FPGA and Verilog.（基于FPGA的流水线CPU）
- **Description**: This is a Verilog implementation of pipeline CPU on FPGA board.
- **Primary Language**: Verilog
- **License**: Not specified
- **Default Branch**: master
- **Homepage**: None
- **GVP Project**: No

## Statistics

- **Stars**: 1
- **Forks**: 0
- **Created**: 2022-08-26
- **Last Updated**: 2023-12-13

## Categories & Tags

**Categories**: Uncategorized

**Tags**: None

## README

# Pipeline CPU based on FPGA and Verilog.（基于FPGA的流水线CPU）

#### 介绍
This is a Verilog implementation of pipeline CPU on FPGA board.

#### 软件架构
本项目为基于Verilog开发的运行于FPGA板上的流水线CPU，共支持38条指令。

#### 参与贡献

1.  Fork 本仓库
2.  新建 Feat_xxx 分支
3.  提交代码
4.  新建 Pull Request